The present invention relates to fast frequency changing phase lock loops and more particularly, to an improved pre-setting circuit disposed therein for presetting the voltage controlled oscillator of the phase lock loop to improve frequency agile operation thereof.
The embodiment depicted in FIG. 1 comprises the components of an elementary phase lock loop. In general, an elemental loop may include a set-point frequency reference source 10 which may provide a set-point frequency signal 12 to one input of a phase detector 14. The output signal 16 of the phase detector 14 may be provided to a loop filter 18 which conditions the signal to provide a filtered signal 20 which governs the output frequency of a voltage controlled oscillator (VCO) 22. The useful output 24 of the phase lock loop is generally taken from the frequency signal generated by the VCO 22.
Usually in an elementary embodiment, output frequency signal 24 or a signal representative thereof may be coupled to the other input of the phase detector 14 along a feedback path 26. For those cases in which an output frequency other than that generated by the set-point frequency source 10 is desired, a conventional down converter 28 may be disposed in the feedback path along with a signal conditioning circuit 30 generally coupled in cascade therewith. The output signal 32 of the conditioning circuit 30 may then be provided to the other input of the phase detector 14. With this configuration, the output frequency signal at 24 or a frequency signal derived therefrom may be adjusted in accordance with a reference frequency signal 34 which may be coupled to another input of the down converter 28.
Typically, phase lock loops of this type may be in either of two conditions, one being referred to as the non-linear mode which is a condition during which phase lock does not exist and the other being referred to as quasi-linear mode which is a condition that exists after phase lock occurs. Phase lock is generally considered a condition in which the difference between the feedback frequency at 32 and set-point frequency at 12 is sufficiently small enough that the phase lock loop can function as a linear control apparatus.
Generally, there are very few problems which exist in the operation of an elementary phase lock loop having a fixed reference frequency at 34. However, there are those systems which require the reference frequency at 34 to be selectively and rapidly switched between a plurality of reference frequencies to alter the output frequency at 24 accordingly. In these systems, if a rapid change in reference frequency results in a frequency difference which exceeds the bandwidth of the phase lock loop, phase lock will be disrupted.
The object of a fast frequency changing or frequency agile phase lock loop is to quickly arrive at a frequency difference in the phase detector 14 to render a phase error signal at 16 within the bandwidth limitations of the phase lock loop to effect a phase lock condition. If the damping of the phase lock loop is adequate, which is generally the case for low noise microwave phase lock loops, phase lock and settling to less than 0.1 radian phase error usually occurs in time less than 4/.pi.f.sub.N), wherein f.sub.N is the natural frequency of the phase lock loop. As an example, suppose the reference frequency signal at 34 is rapidly selectively switched in frequency by say 20 megahertz, for example, and the phase lock loop bandwidth is only on the order of 100 kilohertz, then phase lock can never occur at the new frequency unless a means is provided to change the setting of the voltage control oscillator at 22 to render a frequency difference at the phase detector 14 which is on the order of 100 kilohertz.
Typically, a phase lock loop system (see FIG. 1) may achieve the aforementioned task by providing a preset coarse tune signal to one port 36 of the VCO 22 and may utilize the filtered phase error signal 20 for providing a fine tuning signal coupled to another port 38 of the VCO 22. With this configuration, a phase lock condition may be determined utilizing a synchronous demodulator 40 and a comparison circuit 42. The precision frequency signal 12 may be phase shifted by 90.degree. using a conventional phase shifter 44 and the resulting phase shifted frequency signal may be supplied to one input of the demodulator 40. An inphase I component of the feedback frequency output of the conditioner 30 may be provided to another input of the demodulator 40. A dc signal 46 may be effected by the synchronous demodulator 40 when the phase detector 14 develops an error of less than .+-.1 radian. Signal 46 is coupled to one input of the comparator 42 and therein compared with a reference signal, denoted as REF, coupled to the other input thereof. At some predetermined comparison condition, an output signal 48 of the comparator 42 may be generate and be indicative of a phase lock condition. This digital signal 48 may be provided to an oscillating integrator circuit 49 to control the coarse tune presetting operation of the VCO 22 by inhibiting the oscillation at the time phase lock is indicated. Once phase lock is established, the quenched oscillating integrator 49 may be governed by the filtered phase error signal 20.
In more specific detail, this typical phase lock loop system may have its reference frequency signal 34 derived from a plurality of crystals 50 switchably selected by a conventional frequency controller 52 via signal line 54 as shown in the embodiment of FIG. 1. The output frequency at 24 of the phase lock loop may then be determined by the selected crystal frequency as controlled by the frequency controller 52. As each new crystal reference frequency is selected, the oscillating integrator 49 is operated to change the coarse tune signal of the VCO 22 to render a phase lock condition of the overall phase lock loop.
A typical circuit for achieving this signal presetting operation is shown within the dotted line block 70 of FIG. 2. The circuit 70 may comprise an integrator I1 and a comparator I2 having its output the other's input connected to with a resistive component. Coupled between the output of comparator I2 and the input of integrator I1 in series with the interconnecting resistive component is an electronic switch S1 for interrupting the signal flow therebetween. The switch S1 may be operated in a closed position at times, when there is no phase lock condition and in an open position, at times, when there is phase lock. The output of the integrator I1 becomes the coarse tune signal for presetting the VCO 22. In addition, the filtered phase error signal 20 may be provided to the oscillating integrator 70 through a buffer amplifier A1 and resistive elements R1 and R2 coupled in series. In this configuration, the other end of R2 may be coupled to the input of the integrator I1 and a second electronic switch S2 may be coupled between ground and the interconnection of R1 and R2. Switch S2 may be operated closed during the out-of-lock condition of the loop and open during a phase lock condition thereof.
In operation, then, as a new crystal reference frequency signal is selected, causing the phase lock loop to be in an out-of-lock condition, the electronic switches S1 and S2 may be rendered closed. In this configuration, the integrator I1 and comparator I2 may operate cooperatively to generate a sawtooth waveform at the coarse tuning port 36 of the VCO 22. During the slow moving slope of the sawtooth waveform, the phase lock loop attempts to achieve phase lock as determined by the synchronous detector 40 and comparator 42. When the phase lock condition is indicated by signal 48, switches S1 and S2 are operated to the open position, thus inhibiting the sawtooth movement of the output of the oscillating integrator 70. In this state, the coarse tune signal is modulated in accordance with the filtered phase error signal 20 provided to the input of integrator I1 through the amplifier A1 and resistors R1 and R2. Accordingly, this operational procedure may be repeated for each newly selected crystal reference frequency.
The foregoing described circuit permitted frequency agile operation by switching the frequency output of the phase lock loop between just a few selectable frequencies utilizing corresponding precision crystal controllably derived frequencies at 50 in FIG. 1. In other applications of the phase lock loop systems, greater numbers of less stable frequencies are sometimes acceptable. In some cases, the number of selectable frequencies specified may be on the order of several hundred. For this purpose, at least one known phase lock loop system employs a reference voltage controlled oscillator 56 (see FIG. 1) to supply the reference frequency 34. The reference VCO 56 may be controlled by the frequency controller 52 utilizing the signal line 58 as shown in the embodiment of FIG. 1. An electronic switch S3 may be included in this configuration to allow the frequency controller 52 to select between the crystal frequency generator 50 and the reference VCO frequency generator 56 to provide the reference frequency signal 34. Because the reference VCO 56 is not considered as stable a frequency reference source as the crystal frequency generators 50, it is generally well understood that periodic calibration of the VCO 56 will be required for achieving the stabilization figures usually specified.
To accommodate the significantly higher number of switchably selectable frequencies at the output 24 of the phase lock loop described in connection with the complete embodiment of FIG. 1, typically a phase lock loop system may provide for an improvement in the oscillating integrator circuit 49 as illustrated by the overall circuit diagram embodiment of FIG. 2. In this embodiment, the frequency controller 52, which is conventionally a digital data processor, supplies a preset signal to the presetting circuitry 49 via a conventional digital-to-analog converter 60 and signal line 62. In addition, a measuring circuit 64 is included to permit the frequency controller 52 to measure the coarse tune signal being applied to the VCO 22. The measuring circuit 64 interfaces with the frequency controller 52 utilizing the signal lines 65. An additional logic signal 66 is provided by the frequency controller 52 to a block of logic shown at 68. The resulting output signals of the logic block provide switch control of the oscillating integrators of the embodiment of FIG. 2.
Referring to FIG. 2, the embodiment includes a second oscillating integrator 72 which comprises an integrator I3 and comparator I4 coupled together in a similar circuit configuration as that of the oscillating integrator 70. Between the output of comparator I4 and input of integrator I3 are disposed two electronic switches denoted as S4 and S5. In addition, a connection is provided from the common connection of resistors R1 and R2 to the input of integrator I3 utilizing a resistive element R3. In this embodiment, the phase error signal 20 may be coupled to both oscillating integrators 70 and 72 for control of the one which is selected for use.
Because the phase lock loop may be operated in either fast agile or slow agile mode, a single-pole-double-throw electronic switch 74 may be included having the outputs of the oscillating integrator 70 and 72 coupled to respective switch positions thereof and having the pole position coupled to the coarse tuning port of the VCO 22. The switch 74 may be operated by a digital signal, denoted as FRAGIL, generated by the frequency controller 52 via inverter 76. Accordingly, when the slow agile mode is desired switch 74 may be operated to position 1 by one state of the logical signal FRAGIL. Conversely, when the fast agile mode is desired, the switch 74 may be operated to position 2 as governed by the complement of the logical signal FRAGIL. The switches S1, S2, and S5 may be operated by the logical combination of the signals FRAGIL and LOKBIT which is the signal 48 generated at the output of comparator 42.
More specifically, the complement of LOKBIT, effected by inverter 78, is utilized to operate switch S2 in a closed position. Switch S1 is controlled to a closed position as a result of the "AND"ing of signals FRAGIL and LOKBIT. Similarly switch S5 is operated to a closed position as a result of the "AND"ing of signals FRAGIL and LOKBIT. The aforementioned signals controlling switches S1 and S5 are generated by two AND gates 80 and 82, respectively.
On the other hand, the control of the electronic switch S4 is governed by the circuitry depicted in the dotted block 84 which includes a window comparator at 86 and a flip flop 88. The output signal 90 of the flip flop 88 provides the signal to operate switch S4. The window comparator configuration includes two comparators C1 and C2. The minus input of C1 and plus input of C2 are tied together and connected to the output of integrator I3 through a resistive-capacitive filtering arrangement shown at 92. The analog preset signal 62 generated from the D/A converter 60 is provided to the plus input of C1 through an electronic switch S6 and is additionally provided to the minus input of C2 through another electronic switch S7. Coupled between switch S7 and the minus input of C2 is an offset voltage source V1 having its positive terminal connected to the switch and negative terminal connected to the input. In addition, the plus input of C1 is connected to ground through an electronic switch S8 and the minus input of C2 is connected to the minus reference through another electronic switch S9. The electronic switches S6, S7, S8 and S9 are governed in their operation by the logical signal denoted as CALIN generated from the frequency controller 52. More particularly, switches S8 and S9 are operated to their closed position by the signal CALIN and the switches S6 and S7 are operated to their closed positions by the complement of the signal CALIN, (i.e. CALIN). The outputs of the comparators C1 and C2 are coupled to the clock and preset inputs of the flip flop 88, respectively. The output signal 90 of the flip flop is then coupled to the electronic switch S4 for operation thereof.
The measuring circuit 64 includes a conventional sample and hold circuit comprising a buffer amplifier A2 and another amplifier A3 with a sampling switch S10 disposed therebetween. The output of A3 is coupled to the inverting input of A2. Also included in the circuit 64 are two signal-pole-double-throw switches S11 and S12 having the first positions thereof coupled together. The second position of switch S11 is coupled to the non-inverting input of the buffer amplifier A2 and the pole position thereof is coupled to the filtered output of the integrator I3. The second position of switch S12 is coupled to the analog preset signal 62 and the pole thereof is coupled to one input of a conventional comparator circuit C3 also included in the circuit 64. The other input of the comparator C3 is coupled to the output of the amplifier A3. The digital signals denoted as SAMPLE, VCOCAL and GUNCAL, generated by the frequency controller 52 over signal lines 65, govern the operation of the electronic switches S10, S11 and S12, respectively. The output of comparator C3, denoted as CALOUT, is provided to the frequency controller 52 as an indication of a predetermined comparison condition.
In a typical operation of the embodiments depicted in FIGS. 1 and 2, when in the slow agile operational mode, the switches S3 and 74 are appropriately positioned. The frequency controller 52 selects the desirable crystal frequency reference signal which is coupled to the reference signal input of the down converter 28 via switch S3. Concurrently, switch S1 in the oscillating integrator 70 is closed causing the output integrator I1 to oscillate in a sawtooth waveform thus governing the frequency output of the VCO 22 accordingly. When a phase lock condition is established, as indicated by the digital signal 48 denoted as LOKBIT, switches S1 and S2 are both opened. Thereafter the filtered phase error signal 20 is used to govern the output of the integrator I1 for governing the output frequency of the VCO 22.
On the other hand, when the phase lock loop is in the fast agile mode of operation, switches S3 and 74 are both switched to position 2 and thereafter, the frequency controller 52 selects the reference frequency signal from the reference VCO 56. In this mode, the output of the oscillating integrator 72 is used to govern the coarse tune voltage of the VCO 22. Switches S6 and S7 of the window comparator 86 are governed to the closed position applying an appropriately chosen preset signal to the plus and minus inputs of comparators C1 and C2, respectively. Electronic switches S4 and S5 are operated to their closed position until the output of the integrator I3 falls below the preset value at which time the flip flop 88 is clocked and the resultant signal 90 causes the switch S4 to open. The output of integrator I3 continues to fall but at a much slower ramp rate until phase lock is achieved. At the phase lock event, switches S2 and S5 are opened thus providing for governing of the integrator I3 by the filtered phase error signal 20. Should phase lock not occur during a slow ramping cycle of the oscillating integrator 72, the filtered output voltage thereof will fall below the reference voltage of the comparator C2 which renders the output 90 of the flip flop 88 in a state to cause the electronic switch S4 to close starting again the fast ramp cycle of the sawtooth waveform. The fast and slow ramping cycles of the sawtooth waveform may continue cyclically until phase lock is achieved.
As indicated above, with the use of the reference VCO 56 for the setting of the number of switchable selectable output frequency settings desired, the frequency controller 52 must be initially calibrated for the output preset signals 62 and respectively corresponding settings of the reference VCO 56 and thereafter, calibrated from time to time to ensure fast phase lock conditions after a frequency change. A typical calibration procedure may include switching in at prespecified times each one of a plurality of crystal reference frequencies through switch S3 to the down converter 28 as controlled by the frequency controller 52. At each crystal reference frequency setting, the corresponding setting for the reference VCO 56 over digital lines 58 is determined. An illustration of this procedure is depicted in the graph of FIG. 3. On the abscissa, three crystal reference frequencies, as an example case, are marked off and denoted as #1, #2, and #3. In the calibration procedure, the first reference crystal frequency is coupled to the down converter 28 through switch S3 and the digital signal CALIN is made positive thus closing switches S8 and S9. As a result, the window for the comparators C1 and C2 ranges from ground to the minus reference. Consequently, the output of the oscillating integrator 72 is caused to move at the slow ramping rate within the window in one direction and at the fast ramping rate in another direction in accordance with the operation of switch S4.
During the times when there is no phase lock, switches S2 and S5 are held closed. At phase lock, switches S2, S4 and S5 are all in the open position and the output of integrator I3 is sustained substantially by the filtered phase error signal 20. Thereafter, switch S11 is controlled to position 2 in accordance with the state of the logical signal VCOCAL and switch S10 is closed in accordance with the state of the logical signal SAMPLE to store the resulting output signal of integrator I3 at the output of the amplifier A3 which is coupled to one input of the comparator C3.
Next, switch S3 is controlled to the position 2 and the reference VCO 56 is preset to a frequency level relatively equal to the first crystal frequency level (refer to FIG. 3). The process is repeated until phase lock is achieved at the preset value of the reference VCO 56. At this time switches S11 and S12 may be in position 1 as controlled by the logical signals VCOCAL and GUNCAL, respectively. The output of integrator I3 may thus be compared with the previously stored output utilizing the comparator C3. During the phase lock condition, the setting of the reference VCO 56 may be incrementally adjusted with the digital line 58 by the frequency controller 52 until the voltage output of the integrator I3 is moved to a voltage level substantially close to that which has been previously stored at the output of the integrator path A3. The digital signal, denoted as CALOUT, provides to the controller 52 an indication as to when the desired comparison condition of comparator C3 is achieved. When this occurs, the frequency controller 52 stores the digital setting F1 of signal lines 58 in an appropriately chosen memory location whose address corresponds to the crystal frequency #1 setting. This same procedure may be repeated for as many crystal reference frequencies which are being used. As shown by the example of FIG. 3 there are three crystal frequencies and three digital data settings F1-F3 respectively corresponding thereto.
In another calibration procedure, preset signals are calibrated in relation to their corresponding reference VCO frequency settings. Initially, the logical signal CALIN is controlled to a state to open the switches S8 and S9 and close S6 and S7. A predetermined initial value for the preset signal is supplied to the inputs of the comparators C1 and C2. Switch S3 is governed to position 2 and an initial setting is applied to the reference VCO 56 over signal lines 58. The initial setting may be that previously determined for the reference frequency F1 (refer to FIG. 3). An illustration of this calibration procedure is provided through the exemplary graph depicted in FIG. 4.
With the reference frequency signal at 34 set at frequency F1 via VCO 56, lines 58 and frequency controller 52, the oscillating integrator 72 is permitted to operate with its sawtooth ramping function until phase lock occurs. Switches S11 and S12 are operated to their second positions in accordance with the states of their logical control signals. Shortly after phase lock, the output voltage of integrator I3, which is the coarse tune voltage of the PLL VCO22, is captured at the output of the sample and hold amplifier A3. Next, the frequency controller 52 varies the preset signal through the D/A converter 60 which is provided to the other input of the comparator C3 through the switch S12. In comparator C3, the varied preset signal is compared with the captured signal on A3 and when a predetermined comparison condition is effected, the output signal CALOUT provides an indication to the frequency controller 52. Upon reception of the comparison indication, the controller 52 stops adjusting the preset signal and memorizes the current digital signal supplied to the D/A converter 60. This digital signal may be representative of the voltage V1 corresponding to the frequency F1 as shown in FIG. 4.
Now, with the preset signal V1 applied to the comparators C1 and C2 and after a time increment .DELTA.T1, the reference VCO56 is set at a new frequency setting, say .DELTA.F away from F1, for example. As a result of the resetting of the reference VCO frequency, the coarse tune voltage is caused to move in proportion therewith to maintain phase lock in the phase lock loop. The new coarse tune voltage (output of I3) is again captured at the output of sample and hold amplifier A3. Thereafter, frequency controller 52 again varies the preset signal via D/A converter 60 until it receives another comparison indication from C3. Upon reception, the digital signal to the converter 60 is stored in a memory location corresponding to the frequency setting of the reference VCO. This new digital signal is representative of the preset voltage level V11 as shown in the exemplary graph of FIG. 4. Accordingly, the reference VCO56 may be incremented at appropriate time intervals and a corresponding preset voltage may be determined for each new setting as shown illustratively by the exemplary graph of FIG. 4.
Once the calibration procedures just described have taken place, the phase lock loop such as that embodied in FIG. 1 may be controlled to selectively and rapidly switch frequencies at its output in either a slow agile or fast agile mode of operation. It is understood that from time to time another calibration may be required because of time and temperature effects on the various phase lock loop system elements.
As in all present designs, there is always room for improvement. In these types of fast frequency changing phase lock loop designs considerable simplification of circuitry is continuously sought as well as greater reproducible and reliable performance especially in the operations of fast frequency switching and phase lock. The emphasis, in the instant application, is directed to reducing the amount of hardware while improving the reliability and reproducibility in production units especially with respect to the speed at which phase lock is attained. Thus, it is the purpose of the present invention as described by the specification to provide for an improved phase lock loop system particularly in the area of presetting the coarse tune voltage of the PLL VCO for fast frequency changing operations in both of the slow and fast agile modes.